This invention generally relates to the manufacturing of integrated circuit chip wiring structures, especially dynamic random access memory (DRAM) chips, and more specifically relates to a method of producing these chips without the use of vias between some layers, while still providing cross-over and contact capabilities.
Integrated circuit (IC) chips, for example dynamic random access memory (DRAM) and static random access memory (SRAM), require different resistance and capacitance limits in the cell array wiring and the sense amplifier/decode and support circuits. In the array wiring, the conductor is customized for low capacitance. For example, in a typical 4 Megabit(M) DRAM the capacitance (C) is less than or equal to (xe2x89xa6) 0.15 femptofarads per micron (ff/xcexcm) in bitline-to-bitline wiring at the expense of resistance (R), which is less than or equal to 1 ohm per square (xcexa9/xe2x96xa1). On the other hand, in the supports and decode circuits (the logic circuits), the resistance is optimized (Rxe2x89xa60.07 xcexa9/xe2x96xa1), while capacitance is less crucial (Cxe2x89xa60.25 ff/xcexcm).
In order to achieve these resistance and capacitance limits, the pitch, which is defined as the width of the line plus the space between the lines, of the wiring structure must be carefully controlled. In order for the wiring to be suitable for the array requirements (capacitance and resistance), the pitch must be as near as possible to the smallest photolithographically achievable size (minimum pitch). Although some minimum pitch wiring is needed in the supports, for the most part the logic circuitry has a pitch about two times the minimum pitch in order to carry the signals with the requisite lower resistance. Various ways of creating the necessary line widths have been suggested. See Cronin, J. and C. Kaanta, xe2x80x9cThickness Controlled Thick and Thin Lines in One Damascene Levelxe2x80x9d, IBM Technical Disclosure Bulletin (TDB) No. 7, at 393-94 (Dec. 1990); Cronin, John, xe2x80x9cMethod to Make Thin and Thick Lines Within a Single Level of Damascene Wiring Using a Single Photomaskxe2x80x9d, IBM TDB No. 7 at 387 (Dec. 1990); Cronin et al., xe2x80x9cOptimum Metal Line Structures for Memory Array and Support Circuitsxe2x80x9d, IBM TDB Vol. 30, No. 12, at 170-71 (May 1988); Cronin et al., Method for Obtaining Low Resistance and Low Capacitance Metalization (Sic) Using Single Metal Deposition, IBM TDB Vol. 30, No. 12, at 142-43 (May 1988); and Anonymous, Process to Make Thick and Narrow Conductive Lines, IBM Research Disclosure, No. 313 (May 1990)
As shown in FIG. 1, the necessary line widths were initially constructed by depositing and defining a first metal layer Ml that was thin, covering the first metal layer M1 by depositing a layer of an insulating material I, followed by depositing and defining a second metal layer M2 that was thick. Contacts between the first and second metal layers M1, M2 were formed by etching a tapered via V through the insulator I and then depositing the second metal layer M2 over the insulator I. Thus, contact was made between the first and second layer M1, M2 through the tapered via V.
It was then found that a planarized layer of insulative material was desirable for improved photolithographic resist image definition (the planar surface minimized depth of field problems). FIG. 2 illustrates the solution wherein a first metal layer (thin) M1 was deposited and defined. The insulator I was next deposited over the entire surface and planarized. Studs S were formed by etching a vertical via V through the insulator layer I, depositing a stud via metal M3 therein, and planarizing the surface. The second metal layer (thick) M2 was then applied and patterned so that connection between first and second metal M1, M2 was made through the stud via S.
As shown in FIG. 3, further improvements to minimize cost by eliminating processing steps and materials were made by combining the stud via metal with the second metal layer M2. In this method, the first metal layer (thin) M1 was defined and deposited followed by an insulator layer I which was deposited and planarized. The second metal layer""s M2 wiring lines in the insulator I were defined as trenches T and stud vias S were defined as holes H. Metal was deposited to fill the trenches T and holes H and the metal was then planarized. (see also FIG. 13). By defining the trenches T first and then the studs S, before metallizing, the one metal deposition filled both the trenches T and holes H thereby saving costs. This approach to wiring is known as the xe2x80x9cdamascene approachxe2x80x9d.
The xe2x80x9cdamascenexe2x80x9d approach to wiring is well known in the industry. It comprises depositing an insulator over the semiconductor device structures, e.g. M1. Next, the insulator is planarized by a chemical-mechanical polish (CMP) process. A resist material is applied, exposed to an energy source, and developed, leaving openings in certain regions. These openings define wiring channel regions/trenches. The insulator exposed in the resist openings is subjected to a reactive ion etch (RIE) to remove the exposed areas of insulator. The remaining resist material is then removed, leaving the planar insulator with channels or trenches cut into it. A conformal metal is applied over the entire surface, filling all the trenches and covering all the insulator surfaces. The metal is removed by a planarization, e.g., a CMP, process. The metal is only left in the trenches, forming wiring channels.
Adding a via level requires extra layers which must be sequentially defined. Each additional step to the process requires another alignment step, which increases the likelihood of failure of the final product. Additionally, each processing step requires further handling of the chips which increases cycle time. By reducing the number of steps and layers, there is a reduction in handling and delays, which also tends to increase the yield of the chips because there are fewer defects introduced through handling. In addition, yield is enhanced by the elimination of process variables related to the uncontrolled delays which are created when the chips are processed with several extra steps in the production line. The processing characteristics of the materials used in the production of the chips can vary depending on extent of time elapsed from one processing step to the next. By reducing the number of steps, these delays are reduced and more repeatable, thus reducing process variability. These increases in yield result in cost savings to the manufacturer. Additionally, the removal of the intervening insulator results in cost savings both because of the reduced material costs and because of the reduced handling costs.
In the manufacture of dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) chips, containing the costs of production is essential. One way of reducing cost is to eliminate as many process steps as possible. One possibility is to eliminate a separate, trapped via level between the first metal and the second metal, if possible. Typically the first metal is a thin layer while the second metal is thick. Since the thin metal is required only in the DRAM array for low capacitance and the thick metal is required in the supports for low resistance, one could limit the design rules so that a cross-over between the thin and thick lines is not required and therefore a via connection between the thick and thin layers is not required. However, it should be noted that a via level between two wiring levels allows the two levels to cross each other, and connect when a via is defined at the cross-over, but not connect if there is no via at the cross-over.
FIGS. 4 and 5 show two variations of an approach called the xe2x80x9cmulti-damascenexe2x80x9d approach, that create thick and thin wiring levels without both a separate, trapped via level and cross-over capability. The method, as shown in the FIGS. 4 and 5, creates thin lines M1 by the damascene method in a thin insulator Ithin, followed immediately by a second, thick line M2 in a thick insulator Ithick by the damascene method. Where the thin and thick lines M1, M2 cross, at the intersection, they electrically connect C. A via which is normally used between the thin line and the thick line, is left out, since crossing over without connection is not needed in the DRAM design case. By removing the intervening insulator and via connection level, cost is reduced. However, there are times in more complex, logic intensive DRAMs (high density synchronomous DRAMs and video DRAMs) when some amount of cross-over is necessary.
That is, standard interconnection systems use two levels of damascene, a first level and a second level. These levels are insulated from each other by an intervening insulator material. When a second level crosses over a first level, no electrical connection is made because the levels are insulated from each other by the intervening insulator. When electrical connection is required between the first and second level, a conductive via is defined in the intervening insulator at the intersection where electrical connection is to be made. This gives the designer total wiring flexibility and is, therefore, more desirable than the previous instance, in which every time crossover occurs, there is electrical connection.
Other ways of obtaining thick and thin lines were explored including, manufacturing the chip to have the thick and thin lines in different areas of the chip, so they were decoupled from each other. The lines were either manufactured as part of the same plane, as shown in IBM TDB Vol. 30, No. 12 at 142-43 (May 1988) or, using various methods, as a thick portion and a thin portion in different planes, as discussed above. Typically, wherever the lines were there was no via between them. On the other hand, whenever connections were needed, the vias were used with a layer of an insulative material between the two metallization planes. As can be seen, the methods described of creating the thick lines in one area and thin lines in a different area either: a.) consume a lot of xe2x80x9creal estatexe2x80x9d on the chip surface or b.) do not allow cross-over unless an intervening insulative layer is used, in which case the vias were necessary.
There exists a need for a structure in which the second level is normally insulated from the first level at cross-overs, but a via would not be required when the electrical connection of the thin and thick lines was desirable. This specific case occurs in DRAM and SRAM circuits, where two wiring levels are needed for electrical design considerations, i.e., low capacitance (thin) array wiring and low resistance (thick) support wiring. These thick and thin levels are defined by the damascene technique. When some insulated cross-over of thin and thick lines is needed, particularly in those regions between arrays and for running thick power buses in the array, it would be most effective to do so without the need for an entire level of via wiring (insulator/mask/via/conductor). Fortunately, these insulative cross-over regions do not require the layout considerations (density) that adding a via would allow for. Therefore, a method for wiring thin and thick wires with some low density (large layout area) cross-over capability is needed.
The present invention is a novel integrated circuit (IC) chip wiring structure and the method for producing it. The IC chip""s wiring structure is laid out in such a manner that the thick or low resistance plane may cross over the thin or low capacitance plane by manipulating the design of the interconnect structure and/or device layout on the substrate. The use of vias, with the associated mask alignment problems, processing steps and associated costs, is obviated by this new method of applying the various layers to the substrate surface.
The method consists of using an already existing underpass and designing the metal levels. This process is performed simultaneously with the contact layer metal. A main layer of wiring and passivating material is then applied, which may be thick or thin but is typically a thin layer, with some of the connections being made by simple overlap with the metallized areas of the contact metal. The contact metal connections would be utilized whenever crossover without contact with a third or upper layer was desired. The third layer, typically of the opposite thickness of the main layer, is then applied, patterned, and etched in the desired areas. The third layer is metallized and all crossover areas for the main layer should then be complete, the passivating areas of the main layer insulating the first layer from the third layer. The third layer can crossover the contact layer without xe2x80x9ccontactxe2x80x9d.